In electronic data processing systems, there has been increasing interest in semiconductor integrated circuits for computing logic functions, using both n-channel (NMOS) and p-channel (PMOS) enhancement type field-effect transistors because of the improved noise and low power dissipation properties of such circuits. Hereinafter it should be understood that all of the transistors mentioned are enhancement mode unless otherwise indicated.
In a fully complementary CMOS circuit having logic gates in which each PMOS transistor in a given gate is paired with a corresponding NMOS transistor, the logic function of each such logic gate is completely implemented twice, once in an array of PMOS transistors and again in an array of NMOS transistors. The advantage of using the two complete arrays is that, except for the brief time interval during which the outputs or inputs are making transitions, no current flows in the circuit and hence no power is consumed. However, one disadvantage of this approach is the large amount of semiconductor area needed to accommodate the two complete arrays of transistors. Moreover, the extra area and the extra transistors required for the two arrays result in a large capacitive load which undesirably slows the speed of the circuit.
Accordingly, fully complementary CMOS technology has not proved particularly popular. Instead, NMOS technology early became the dominant technology for high speed logic, particularly since an NMOS transistor has a better figure of merit than a PMOS transistor because of the higher mobility of electrons in NMOS than holes in PMOS transistors. On the other hand, as the source to drain distance and hence the channel length of individual PMOS and NMOS transistors is reduced to submicron (about a micron or less) size, the difference in speed and hence in figure of merit between NMOS and PMOS transistors becomes of less importance. However, power dissipation can become a problem in large arrays implemented in either NMOS or PMOS technology.
To retain the main benefits of CMOS technology without the area penalty of complete duplication of the two arrays, workers in the art have developed the circuit technique known as pseudo-NMOS. Pseudo-NMOS technology is a circuit design technique which uses circuits identical to those in NMOS technology except for the substitution of a PMOS pull-up transistor for the load or pull-up NMOS transistor. However, a problem with this approach is that pull-up current always flows in a logic gate of the pseudo-NMOS circuit even when the gate is pulling down, whereby the time required for pull-down is undesirably prolonged. Reducing the pull-up current to a very small value would not solve the problem because then the subsequent pull-up would be correspondingly very slow. As a result, the speed of CMOS and of pseudo-NMOS technology tends to be nearly the same, and the trade-off in choosing one versus the other technology is between the low power of fully complementary CMOS technology and the low semiconductor area of pseudo-NMOS technology.
To achieve circuits which combine both low capacitance and high current capability, various forms of clocked or "dynamic" circuits have been developed. A typical form of such a dynamic circuit--called "dynamic pseudo-NMOS" or "dynamic CMOS"--includes in each logic gate (or "stage") a network (or "cluster") of NMOS driver transistors interconnected to implement a logic function in the same manner as they would be in static NMOS. A PMOS pull-up or "precharging" transistor is connected between the high level (V.sub.DD) power line of the power source and the output node of the network, and an NMOS pull-down or "power switch" transistor connected between the low level (V.sub.SS) power line of the power source, typically ground, and the other or second node of the network of NMOS drivers. In general, by "high level" is meant a voltage level which, when applied to the gate electrode of a driver, tends to turn the transistor on. (Thus, in dynamic pseudo-PMOS--i.e., using PMOS drivers--the "high" or "precharge" level would become the low level V.sub.SS, while the "low" or "ground" level would become the high level V.sub.DD ; the precharging transistor would be NMOS; and the power switch would be PMOS.) In dynamic CMOS operation, the gate electrodes of the pull-up and of the pull-down transistors are clocked together for precharging, so that during each precharge phase of the clock cycle the output node of the network is precharged to essentially the high level, while at the same time the current path from the output node to the low level is open (turned off), regardless of the on-off conditions of the drivers, because the power switch is then off (open). Changing of logic inputs to the network occurs during each such precharge phase. At the completion of the precharge phase, the clock turns off the pull-up transistor to terminate precharging, and turns on the power switch transistor to close the path to the low level and thus to begin the logic computation or "evaluation" phase. Depending upon the high versus low states of the various logic inputs to the various drivers in the network, and hence depending upon the on versus off conditions of the various drivers, the output node will either continue to float at the high precharge level or be pulled down to a lower, essentially V.sub.SS level.
Theoretically, the advantage of a dynamic circuit, such as the foregoing pseudo-NMOS, is that its load capacitance is comparable to that of a pseudo-NMOS circuit, but the full pull-down current is available with the result that fast speeds can be realized. Problems arise, however, in realizing these supposed speed advantages in practical circuits, because such circuits generally have several logic networks or "stages" in tandem. In the dynamic approach no such stage can be activated to the evaluation phase until all inputs to that stage have stabilized--i.e., have become valid. Thus, the time allotted for the stages to stabilize must be chosen so that even the stage with the longest delay can stabilize. Moreover, stabilization is complicated because in any given stage (excepting the first stage) any driver coupled to the output node of a preceding stage begins the evaluations phase with input at the high precharge level of the output node of that preceding stage, and hence that driver tends to discharge the output node of the given stage. Accordingly, it is often necessary to include some provision for some delay in the commencement of the evaluation phase of different drivers of the circuit. But this provision results in considerable increase in circuit complexity, particularly when many stages are involved.
One approach that has been developed has been the CMOS domino logic circuit. In its preferred form, each stage in this technology utilizes clusters of NMOS driver transistors for implementing the logic networks and clocked PMOS pull-up transistors for implementing precharge or load elements--all transistors interconnected between a high power terminal connected to a high voltage level power line (V.sub.DD) and a low power terminal connected to a low voltage level power line (V.sub.SS). As in a dynamic pseudo-NMOS circuit, during each precharge phase of the clock, every output node is precharged high while the path to the low level, typically ground, is kept open by means of the off state of a power switch supplied by a clocked NMOS transistor; and the precharge phase is terminated when the power switch is turned on and hence the path to ground is closed. A significant characteristic of the domino CMOS circuit is that it includes many stages, each stage implementing either the same or a different logic function, and that the transition from precharge to evaluation phase in all stages is accomplished by means of a single clock edge (or its complement) applied simultaneously to all clocked transistors in all stages of the circuit. To prevent spurious input signals during evaluation, it is important to assure that in each stage (excepting the first) the inputs to any drivers which are coupled to a preceding stage are all low before the beginning of the evaluation phase. To this end, a static inverter is included as a buffer between the output node of each domino stage and the input node of the drivers in any succeeding domino stage to be supplied by such output. During the precharge, when the output node of every stage is momentarily at the high precharge level, the corresponding buffer output of every such stage is low, so that all circuit nodes which connect the output of one domino stage to an input node (gate terminal) of a driver in any other domino stage are low and therefore any such driver is off. Thus during each evaluation phase, such an input node of the driver can experience only a single type of voltage swing or transition, namely, from low to high. All such driver input nodes can make such a low to high transition (at most) only during an evaluation phase and then must stay at the same voltage level until the next precharge phase when they again can experience only a single type of transition (if any), in this case from high to low. Of course, such input nodes need not make any transition if they are already at the appropriate voltage level. As a result, there cannot be any spurious signals or "glitches" at any nodes in the circuit. Thus, all stages may be switched from precharge to evaluation phase--i.e., all pull-up transistors may be switched from on to off--by means of the same clock edge. Moreover, if all drivers in a given stage are supplied with properly timed signals--i.e., all of which are low during all precharge phases--then the power switch in the given stage can be omitted. The voltage developed at the output node of any stage is automatically itself a properly timed signal in this sense.
A domino CMOS logic circuit ideally has a desirably low power consumption since there is never a closed d.c. path from the high level of the power source (V.sub.DD) to ground (V.sub.SS). Also, the full pull-down current is available to drive the output nodes. At the same time, the load capacitance is much smaller than that encountered in the standard static CMOS circuit because the cluster of complementary driver transistors have been eliminated. Meanwhile, the use of a single clock edge to activate the entire domino CMOS circuit provides simple operation and full utilization of the speed of each stage.
To avoid undesirable sharing of charge between the output node of a given stage and one or more nodes between drivers of that stage mutually connected in series, auxiliary precharge pull-up transistors can be added for directly precharging such nodes and thus for preventing them from undesirably taking away charge from the output node during evaluation. Such undesirable sharing can otherwise occur when some (but not all) the drivers experience off to on transitions during evaluation.
One limitation of domino CMOS is that the output of each but the last stage must be buffered with an inverter. This requirement of buffering inverters can undesirably consume precious semiconductor area.
In order to obviate the need for the buffering inverters between successive stages of a domino CMOS logic circuit of the form described above, successive stages of a domino CMOS alternate between dynamic pseudo-NMOS and dynamic pseudo-PMOS, i.e., successive stages alternate with purely NMOS and purely PMOS driver transistor clusters, and correspondingly alternate with PMOS and NMOS precharging transistors, respectively. All stages are timed by the same clock edge (or its complement). In addition, in case the input signals to the NMOS (or PMOS) driver transistor of any stage are not necessarily always low (or high) during all precharge phases--i.e., are not properly timed--then an NMOS (or PMOS) power switch transistor is added to that stage. Thus, for example, in a two-stage embodiment, the first stage of the circuit contains solely NMOS drivers together with a PMOS precharge transistor and an NMOS power switch, and the second stage contains solely PMOS drivers with an NMOS precharging transistor and a PMOS power switch. Moreover, in any situation where it is arranged that all the input signals for a given stage are properly timed (i.e., such as to maintain all drivers in that stage in the off condition during the evaluation phases), then the power switch transistor can be omitted from that stage. Such a situation occurs, for example, whenever all such input signals are output signals of another stage having driver transistors all of opposite type from that of the given stage and having its precharge transistor(s) controlled by the same clock edge as that which controls the precharge transistor of the given stage.
In many circumstances in data processing systems, it is desired to implement the multiple AND logic function, that is, the AND function of a multiplicity of input logic variables, n in number. For example, if n=4--and there are thus four logic input variables A, B, C, and D--then it is desired to have an electrical circuit with input signals corresponding to A, B, C, and D such that the output of the circuit is at a high voltage level (logic 1) if and only if the signals A and B and C and D are all high; otherwise, the output should be at a low voltage level (logic 0) whenever any one or more of the input signals is at a low voltage level. In addition, the logical inverse or complement of the AND function is called the NAND function, that is, in which a logic 0 for the AND function becomes a logic 1, and a logic 1 for the AND function becomes a logic 0. Since the difference between the AND function and the NAND function is only an inverter, these two names are interchangeable in the discussion below.
As known in the art, a multiple AND logic circuit element for implementing this function can be formed by a single dynamic pseudo-NMOS stage containing a logic cluster of a multiplicity of NMOS drivers whose source-drain current paths are all connected mutually in series. That such a gate implements an AND function can be seen from the following considerations. If the input to any one (or more) of these drivers is low (logic 0) during evaluation and hence that driver is off, then during evaluation the electrical path from the output node of that stage to ground (V.sub.SS) is open and hence the output node remains high (logic 1) at its precharge phase level. On the other hand, if all inputs to the stage during evaluation are high (logic 1) and hence all drivers are on, then during evaluation the path from the output node to ground is closed and hence the output node goes to ground (logic 0) during evaluation. Thus the multiplicity of NMOS drivers mutually connected in series indeed implements the AND function; that is, the function is logic 1 if and only if all input variables are logic 1. Such a circuit element suffers from the problem that the required number of drivers connected in series is equal to the number n of input variables. On the other hand, owing to the resistance R of each driver's channel and the capacitance C of each internal node to semiconductor substrate ground (V.sub.SS), the time it takes for the output node to discharge if and when all drivers are on during a given evaluation phase increases quadratically with the number of drivers, simply because the discharge of a node through a transmission line of identical RC elements in series, n in number, is governed by a diffusion-type equation and is therefore substantially equal to RCn.sup.2. See, for example, C. Mead and L. Conway, Introduction to VLSI SYSTEMS, 1980, pp. 22-23. Thus, in order to implement a multiple AND circuit by means of n drivers mutually connected in series, the required time duration of each evaluation phase becomes unduly prolonged, and hence the speed of operation becomes undesirably slowed, as the number n of input variables increases above three or four. The higher the value of n, the slower the speed. A similar problem of unduly long evaluation phase arises when implementing a logic network for computing other logic functions of more than three input variables in case the network contains any current path through more than three driver transistors connected in series, such as a carry look-ahead for three bits or more of an arithmetic logic unit. The problem is even more serious, of course, in case there are more than four drivers in series.
Thus, it would be desirable to have a logic circuit for performing the multiple AND function, as well as other functions for four or more input variables, which does not require such a long time duration for evaluation.
Moreover, when thus implementing the multiple AND function of n input variables A, B, C, and D by means of a logic circuit containing a multiplicity of n drivers whose current paths are mutually connected in series, it requires a separate circuit to implement the multiple AND function of fewer than n of the same input variables, such as the AND function of AB, or the AND function of ABC. Therefore, it would be desirable to have a circuit for implementing the AND function of n input variables in such a manner that the circuit contains internal nodes at which signals corresponding to the AND function of fewer than the n input variables are developed.